The invention relates to zener zap devices for use in trimming circuits and, in particular, to a zener-like trim device built in polysilicon.
Trimming is a technique used to improve the accuracy and yield of precision integrated circuits. Specifically, after an integrated circuit has been fabricated and tested, trimming is sometimes carried out to modify the performance of the integrated circuit. For instance, trimming may be used to adjust electrical parameters of an integrated circuit to bring those parameters to within specification. Trimming can also be done to adjust the offset voltage of an operational amplifier, or to adjust the absolute value of a reference voltage, or to fine tune the delay time in a chain of logic gates.
Widely used trimming techniques include laser trimming of thin film resistors or xe2x80x9czener zapxe2x80x9d anti-fuse trimming. The zener zap trimming method has gained wide acceptance because, among other things, zener zap trimming is field programmable and is less costly to implement. Furthermore, zener zap trimming can be carried out at the wafer level or after packaging of the die. Therefore, zener zap trimming can be used to compensate for performance variations introduced by packaging of an integrated circuit.
Zener zap method uses zener diodes (also referred to as zener zap diodes) having a low to moderate breakdown voltage as the trim devices. Typically, a trim circuit includes a string of zener zap diodes and a corresponding string of resistive elements where each zener zap diode is connected in parallel with a respective one of the resistive elements. In operation, the zener zap diodes are biased so that they behave as an open circuit as fabricated. When trimming is performed, the zener zap diode is zapped and the junction is short-circuited. Typically, the resistance across the diode reduces to about 10xcexa9 which is treated as equivalent to a xe2x80x9cshort circuit.xe2x80x9d By shorting out selective zener zap diodes and thus the associated resistive elements, a desired change in resistance value can be obtained.
In general, zener zap diodes are formed as a p-n junction of a heavily doped n+ diffusion and a moderately doped p diffusion. The doping level in the more lightly doped p-type diffusion usually determines the junction breakdown voltage. The higher the doping, the lower the breakdown voltage. For cost savings, zener zap diodes are usually constructed using existing layers and diffusions in the CMOS or bipolar fabrication process in which the diodes are to be incorporated. It is common to use the emitter-base junction of a standard NPN transistor device as the zener zap element. FIG. 1, including FIGS. 1(a) and 1(b), illustrates a conventional zener zap diode structure, as disclosed by George Erdi in, xe2x80x9cA Precision Trim Technique for Monolithic Analog Circuits,xe2x80x9d IEEE journal of Solid-State Circuits, Vol. SC-10, No. 6, December 1975. FIG. 1(a) is a top view of the zener diode while FIG. 1(b) is a cross-sectional view of the zener diode. As shown in FIG. 1(b), conventional zener zap diodes are typically formed as NPN transistors in bulk silicon.
Conventional zener zap devices usually require zap currents of 100-200 mA for a duration of a few milliseconds to fuse the device. Currently, there has been considerable interest in trimming devices that use low zap currents, such as current values that are much less than 100 mA. Low-zap-current trim devices are of interest primarily for two reasons.
First, low-zap-current trim devices facilitate the use of a serial-register trimming scheme where the number of bond pads required to connect to the trim devices can be considerably reduced. In conventional zener zap trim circuits, at least one bond pad must be provided for each zener zap diode. When precision trimming is desired, such as a 4-bit trim, a large number of zener zap diodes (4-20) are required, making the provision of a bond pad for each diode impractical, particularly when small and low pin count packages are used. Therefore, serial-register trimming is developed where a small number of pads, such as one pad, is used to program a large number of trim devices. In the serial-register trimming scheme, the trimming circuit includes registers and a decoder for storing a serial code received at the bond pad and decoding the code to determine which of a series of zener diodes is to be zapped. Accordingly, one or a few bond pads are needed for programming a large number of zener diodes. In some cases, an existing bond pad can be used for receiving the serial input code so that no dedicated bond pads for the trimming circuit are needed.
However, when the serial-register trimming scheme is used, the same pad is often used to receive the input signals and also to receive the zap currents for programming the trim devices. Therefore, a low zap current and voltage is desired as the transistors in the decoder are typically made small and cannot handle large current or voltage. If the decoder transistors are made large so as to handle a large zap current, the decoder will consume a large amount of silicon real estate, increasing both the size and the cost of the integrated circuit.
Second, low-zap-current trimming devices also facilitate after-assembly trim for improved accuracy. After-assembly trim is preferred because any shift in device characteristics due to the assembly process can be compensated for. As a result, an integrated circuit with very precise operational parameters can be realized.
Conventional techniques to reduce the zap current of trim devices include reducing the n+ to p+ spacing of the zener diode. Variations of the geometrical shapes of the zener diode are also applied. For example, the metal contacts to the n+ and p+ diffusions are moved closer together so that the overall anode to cathode spacing is reduced. It is known that such modification allows a zener zap device built in the silicon substrate to zap at a lower current.
It is also known to form a degenerate or leaky zener where the n+ and p+ regions, formed in bulk silicon, are so closely spaced that they are actually intersected. The degenerate zener can be zapped at low currents to cause a permanent increase in the leakage current. A predetermined amount of increased leakage can be treated as a short circuit.
However, a zener zap trim device capable of being zapped at very low zap current, such as 50 mA or less, is desired.
According to one embodiment of the present invention, a semiconductor device includes a polysilicon layer formed on the top surface of and electrically isolated from a semiconductor structure, a first region of a first conductivity type formed in the polysilicon layer where the first region is heavily doped, and a second region of a second conductivity type formed in the polysilicon layer adjacent the first region where the second region is heavily doped. The first region and the second region form a p-n junction in the polysilicon layer. The semiconductor device further includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region. In operation, a low resistance path is formed between the first metallization region and the second metallization region when a voltage or a current exceeding a predetermined threshold level is applied to a selected one of the first and the second region.
In one embodiment, the voltage or current is applied for zap trimming of the p-n junction where the voltage or current exceeding a predetermined threshold level, together with the resulting current or resulting voltage, provides power sufficient to cause the low resistance path to be formed.
In another embodiment, the polysilicon layer is formed on a dielectric layer formed on the top surface of a semiconductor substrate. The polysilicon layer can be lightly doped with p-type conductivity or lightly doped with n-type conductivity or undoped.